Field of the Invention
Embodiments of the present invention relate generally to integrated circuit fabrication and testing and, more specifically, to performing on-chip partial good die identification.
Description of the Related Art
Oftentimes, in a process known as “partial good die identification,” a silicon manufacturer attempts to identify and disable defective regions of a fabricated die. Subsequently, the silicon manufacturer packages and sells any partially-disabled dies as products or parts having reduced functionality or reduced performance in an attempt to minimize the number of dies that are discarded as defective. To facilitate partial good die identification, chip designers typically implement functional clamps that may be activated to disable specific regions of the chips that are identified as defective. More specifically, when testing the die, if a defective region is identified, then the silicon manufacturer activates the associated functional clamp to disable the defective region.
As part of identifying defective functional regions of dies, a chip designer and/or silicon manufacturer implement test logic that applies test patterns to isolated functional regions within the die and then monitors the response of those isolated functional regions to the test patterns. For small dies, relatively simple test logic may enable the silicon manufacturer to adequately test each die and identify any defective regions in an acceptable amount of testing time. For example, in some implementations, a different pin can be allocated for the testing of each different functional region. As used herein, a “pin” refers to an outer connection of a die and/or a package pin that the outer connection is bonded to as part of the manufacturing process. If the response received via a particular pin does not match the expected response, then the test logic identifies the corresponding functional region as defective. However, as a general matter, the form factors of packages do not increase over time as in proportion to increases in die size. Consequently, as the sizes of dies have increased, the ratio between the number of pins and the size of the die has decreased so much that allocating a separate test pins for testing each separate functional region in a die has become unfeasible.
One approach to identifying defective functional regions in a die when the number of test pins is less than the number of functional regions, involves implementing post processing software in automatic test equipment (ATE) to perform a variety of operations on the response data generated by the die and received via the test pins. However, the time required for the post processing software to determine which functional regions are associated with failing response data may be prohibitive. In particular, because many optimization techniques intermix the data between functional regions and across test pins, identifying the failing functional regions may be complex and exceed the available test time and/or ATE resources, such as memory.
As the foregoing illustrates, what is needed in the art are more effective techniques for identifying defective functional regions within a die.